1. Field of the Invention
The present invention relates to a memory module.
2. Description of Related Art
As a memory device in a memory module used in a main memory (main storage) or the like of an information processing apparatus such as a server, a personal computer, or a workstation, a semiconductor is used. However, since the memory device is formed by a very microscopic circuit, a microscopic defect may occur in production of the memory device. A memory module on which the memory device having the defect is mounted is used in the information processing apparatus, a memory error may occur.
As memory errors, in addition to a hardware defect of the memory device, a software error occurring without any hardware problem, a problem of an interface, a compatibility problem, a contact failure of a socket, an erroneous operation on a memory controller, and the like are conceivable.
In an information processing apparatus which requires reliability of a server often has a function that detects and corrects errors up to a certain data bit rate. A data bit rate which can be corrected depends on the performance of a memory controller.
The error detection and correction are performed by the memory controller, occurring errors cannot be easily classified into errors caused by a problem on the memory module and errors caused by a problem on the other parts. In a system using a plurality of memory modules, a memory module in which a drawback occurs cannot be easily discriminated from other memory modules. A problem of poor reproducibility or a problem that the same drawback cannot be reproduced are also posed, a position where a drawback occurs is often hard to be specified.
For this reason, schemes that detect, correct, and record errors on a memory module are desired.
FIG. 9 is a schematic view of a memory system according to the present invention.
In FIG. 9, reference numeral 1 denotes a memory device; and 2 denotes a circuit board. A memory device 1 is mounted on the circuit board 2 to form a memory module.
Reference numeral 3 denotes a memory controller, and an arrow means transmission of a data signal. In this case, FIG. 9 shows a case in which transmission of a data signal between a memory device and a memory controller is directly performed. The number of data signals, a signal except for the data signal, parts such as a device and a connector related to the signal except for the data signal are omitted.
In the memory system shown in FIG. 9, functions of detecting, correcting, and recording an error are not present in a memory module.
An example of a technique related to a memory module is described in Patent Documents 1 to 4.
In a microcomputer of Patent Document 1 (Japanese Patent Application Laid-Open (JP-A) No. 2002-163243) which includes a flash memory with error detecting/correcting function in which a control program for device-embedded control and control data are input and written from the outside in units of words, and a CPU (Central Processing Unit) that reads the control program and the control data from the flash memory with error detecting/correcting function to execute or output the control program and the control data, the flash memory with error detecting/correcting function selects a plurality of bytes from a word of an external input by external control, writes the bytes, reads the bytes under the control of the CPU, performs error detection and correction in units of bytes, and outputs the bytes.
According to the microcomputer, when a data length of 1 byte is sufficient for the control data, since securement and access of a data area for the control data in units of bytes are performed every bytes per word in units of bytes, a data area reduces to one severalth a data area of a conventional microcomputer, and an unused area in the data area considerably reduces. As a result, a flash memory with error detecting/correcting function is effectively used.
A memory device of Patent Document 2 (JP-A No. 2002-279795) which responds to a command signal, includes: a plurality of banks each configured by a memory array configured to include spare units of a plurality of main storage cells and a plurality of spare storage cells; a  detector to detect an error of a unit of a first main storage cell in a first bank; and a controller that responds to a command signal to automatically re-map the first unit of the main storage cell on the spare storage cell of the first unit.
According to the memory device, a memory device which responds to a command signal includes a plurality of banks of a memory array. Each of the banks includes a plurality of main storage cells and spare units of spare storage cells. The detector detects an error in the unit of the first main storage cell of the first bank. The controller automatically re-maps the unit of the first main storage cell on a unit of a second storage cell in response to a command signal without interrupting access to memory data. As a result, a self-recovering memory which is free from a drawback such as an uncorrectable hardware error in an existing memory scheme and does not require an additional memory module for a spare memory can be provided.
An electric rewritable nonvolatile memory in Patent Document 3 (JP-A No. 6-83716) which mixes high-rewriting-frequency data having a high rewriting frequency and low-rewriting-frequency data having a low rewriting frequency with each other and stores the data, includes: a data identifying unit that identifies data to be written as the high-rewriting-frequency data or the low-rewriting-frequency data; and a data write control unit that writes the data to be written in the memory cell by a predetermined highly reliable method when the data to be written is the high-rewriting-frequency data as a result of the identification of the data identifying unit and that writes the data in the memory cell by a normal method when the data to be written is the low-rewriting-frequency data.
According to the electrically rewritable nonvolatile memory, when the high-rewriting-frequency data and the low-rewriting-frequency data are mixed and stored in the electrically rewritable nonvolatile memory, data is written by a method depending on the rewriting frequencies of the data. For this reason, writing and reading processes having excessive reliability for the low-rewriting-frequency data need not be performed due to the presence of a small number of high-rewriting-frequency data, and a small memory capacity may be advantageously used.
In a main storage apparatus according to Patent Document 4 (JP-A No. 9-288619) which is controlled by a main storage control apparatus including an ECC (Error Correcting Code) circuit built therein and which performs data error detection and correction by using the ECC circuit, a dual-type memory cell is used, an error check unit that is connected to the memory cell and checks an error of data and a selecting unit that selects output data from the memory cell are added, and data is selected by a check result of the error check unit.
According to the main storage apparatus, the main storage control apparatus including the existing ECC circuit built therein is diverted without being changed, and a dualized memory cells are equivalently handled, so that an inexpensive reliable main storage apparatus which, even an error having two bits or more is detected in one memory cell, can continue a process by using other can be provided.
However, in the techniques described in Patent Documents 1 to 4, detection of an error is not performed on the memory module, and error detection accuracy has room for improvement.